Download the MB-Lite to FPGA User Guide: a PDF file.
Code ET4351 Users Guide Delft University of Technology MBL Supplement VHDL version Wishbone Interconnection Architecture compatible Framework V1.0 (Saturday 26th April, 2014) Chapter 1 Design Possibilities For the Ethernet-project, a complete VHDL description of the MB-Lite will be needed instead of the MBL1c-emulator. Furthermore, you need dedicated tools to create a file that can be used for programming an FPGA. As shown in Figure 1.1, it is possible to use only Xilinx ISE to accomplish the whole process, but we prefer to use a separate synthesis tool, i.e. Synplify Pro or Premier, for the first synthesis part. Successful synthesis results in a .edf-file, that also can be processed by the Xilinx ISE tool. On the PCs in our lab, the Synplify Pro synthesizer and the Xilinx ISE platform are available. A successful run through ISE will result in a .bit-file containing the information to program the FPGA. This programming can be accomplished by means of Xilinxs iMPACT program. To enable the .bit-file creation, first some information about the memory usage has to be supplied. This information has to be available in a so-called .bmm-file. The FPGA that we selected is a Xilinx XC3S2000, i.e. a member of the Spartan 3 family of FPGAs. It is mounted on an AVNET Development pcb. Therefore, of course, the tools have to know how to correctly connect the I/O signals to the actual pins of this FPGA. These interconnections have to be defined in a .ucf-file specifically written for our AVNET board that has to be passed to the Xilinx ISE place and route tools. For the Ethernet project, both a .bmm-file and the .ucf-file are available. If it turns out that after synthesis and creation of a .bit-file the c-software for the MB-Lite has to be changed, thanks to the memory information that we supplied, the newly created software program can be loaded directly into the .bit-file. So, there is no need to rerun the complete synthesis and implementation process. This will only be needed if the hardware description has to be updated. 1 2 CHAPTER 1. DESIGN POSSIBILITIES Figure 1.1: Simplified overview of the design flow. Chapter 2 Additions to the ET4351_VHD Package As written before, a real MB-Lite will be needed instead of the MBL1c-emulator. All additional files can be found in the ET4351_VHD_mblite.zip file. A third example SoC has been added, this time containing an MB-Lite, a simple uart, the 8-bit example slave and connections to a number of LEDs. It is recommended to also use this uart in your Ethernet design in order to simplify debugging. The contents of the zip file are intended to be decompressed from your already existing top level directory. The tree that will be added will look like: Figure 2.1 3 4 CHAPTER 2. ADDITIONS TO THE ET4351_VHD PACKAGE 2.1 Contents of ET4351_VHD_mblite.zip The new files are: in the mblite-subdirectory: address_decoder.vhd clk_div.vhd core.vhd core_Pkg.vhd debouncer.vhd decode.vhd ET4351_mblite_Pkg.vhd execute.vhd fetch.vhd gprf.vhd gpr_dsram.vhd mem.vhd mst_wb_adapter.vhd std_Pkg.vhd memory map controller clock divider using parameters for division factor and duty-cycle MB-Lite core unit package defining MB-Lite specific data types, constants, etc. debouncer for a simulated reset button MB-Lite decode unit new package defining data types, constants and common components MB-Lite executre unit MB-Lite fetch unit internal registers for th MB-Litet memory type for the internal registers MB-Lite mem unit interface between data-memory bus and a Wishbone slave package with additional definitions and functions in the ip/uart_AVR8-subdirectory: uart_AVR8.vhd description of the uart in the ip/uart_AVR8/sw-subdirectory: uart_AVR8.c uart_AVR8.h functions for initializing and reading and writing the uart header file with defines specific for the given uart in the example_SoCs/mblite_uartAVR-subdirectory: 2.1. CONTENTS OF ET4351_VHD_MBLITE.ZIP 5 ET4351_mblite_Pkg.vhd sys_ctrl.vhd uart_AVR8.vhd wb_mblite.vhd new package defining all data types, constants, etc. the controller for this design a simple uart with an 8-bit data and address bus description of the processor with a Wishbone interface wb_mblite_uart_soc.vhd the description of the SoC wb_slave_ex8b.vhd the slave used in this example wb_slave_Pkg.vhd the package needed for this slave imem_init.vhd example of initialized instruction memory dmem_init.vhd example of initialized data memory tb_wb_soc.vhd the testbench for this design msim.mpf an example project file for ModelSim wave.do an example of selected signals to be displayed in the example_SoCs/mblite_uartAVR/sw-subdirectory: example.c Makefile mblite.h uart_AVR8.c the program resulting in the given imem and dmem to be used for compiling and linking in this set-up defines for connecting the hardware to the software functions for initializing and reading and writing the uart uart_AVR8.h header file with defines specific for the given uart in the example_SoCs/mblite_uartAVR/rev_1-subdirectory: download_uartAVR.bit the .bit file for programming the FPGA, resulting from the given example SoC in the sw_utils-subdirectory: bin2mem_4x8b.c bin2mem_32b.c bin2vhd_4x8b.c bin2vhd_32b.c bin2vhd_32b_async.c makeit.bat for creating dmem0.mem dmem3.mem memory files for creating the imem.mem memory file for creating dmem_init.vhd for creating imem_init.vhd replacement for bin2vhd_32b_async.c in the original ET4351_VHD release very simple script for creating the executables Files, needed for implementing the design on the Xilinx XC3S2000 FPGA on the AVNET Development boards are provided in the mblite/hw_XC3S2000-subdirectory: mblite.bmm in the boards-subdirectory: description of the BRAMs for this project AVNET_DK_xc3s2000.ucf the .ucf-file needed to obtain a usable .bit-file and in the scripts-subdirectory: 6 CHAPTER 2. ADDITIONS TO THE ET4351_VHD PACKAGE Figure 2.2: Combination of files for simulation, synthesis and implementation. makebit_bmm makemem clean needed for generating a bit file using Xilinx ISE (needs a .edf synthesis file) usable for updating the memory in an existing bitfile removes all kind of (temporary-)files that may erroneously affect a design Finally, in the sw/microblaze-subdirectory some specific Xilinx original microblaze related software can be found, a.o. needed for handling the xil_printf function in the example. 2.2 Setup for the MB-Lite Wishbone slave(s) Combine and create the .vhd-files, e.g. as in the setup for the example SoC as shown below. For synthesis, the wb_mblite_uart_soc.vhd-file will contain the top level architecture with the correct generic parameters to obtain a working implementation. For creating the actual implementation (a .bit-file that can be downloaded into the FPGA), also a definition of the memory blocks is needed (wb_mblite_uart_soc.bmm), as well as a user constraint file (AVNET_DK_xc3s2000.ucf) in which a.o. the connections of the I/O signals to the actual 2.3. SCRIPTS AND UTILITIES 7 FPGA pins are defined 2.3 Scripts and utilities In the scripts directory, a number of utilities can be found that will help automate the computational parts of the design flow. The scripts need a Linux OS shell (either the Bourne or the Bash shell will do), so on Windows machines Cygwin should be the environment to work from. In practice, the scripts will be run from the revision-directory (e.g. rev_1)in which the designs result files have been written. Therefore, copy all shell scripts that reside in the ./scripts directory, as well as the .bmm, the .ucf and the imem_dmem.mem file that resulted from compiling the c-sources to this revision directory. 2.3.1 Generating a .bit file It is assumed that at this point in the design process all simulations suggest that the VHDL code contains no errors and that the SoC will behave as expected. First thing to do now is to create a .edf-file specifically for the XC3S2000 FPGA, either with Synplify Pro or Xilinx XST. Synplify Pro needs a Project in which all filenames and implementation options are defined. This is usually done by creating or building a project from using the program menus and graphical interfaces. In Synplify Pro, adjust the implementation options to select the Spartan 3 Technology, a XC3S2000 Part in an FG676 Package with Speed -4. Perform the synthesis step (Run), until there are no errors. After creating the .edf-file, run the makebit_bmm script in order to generate the .bit-file. syntax: makebit_bmm ediffile [ucffile [prefix]] Note: no filename extentions; edf and ucf files should be in the local directory, i.e. /rev_#. e.g. ./makebit_bmm wb_mblite_uart_soc AVNET_DK_xc3s2000 from /rev_1 Note: the .bmm-file is expected to have the same name as the .edf-file, so you may need to rename the .bmm-file. This command reads the wb_mblite_uart_soc.edf-file, uses the constraints -like pad numbers and timing specifications- from the AVNET_DK_xc3s2000.ucf-file and runs the Xilinx ISE tools (provided there are no errors encountered) upto the creation of a wb_mblite_uart_soc.bit-file in the current directory. The resulting .bit-file can be downloaded to the AVNET board using Xilinx iMPACT program. 2.3.2 Writing data into predefined memory In case the memories for the MB-Lite have to be updated without a hardware change, the method of using initialized VHDL files is not very flexible. For each set of new data, the whole process starting with the synthesis step has to be re-executed. Fortunately, there is a possibility to predefine an empty block of memory to be created in the .bit-file, that can be filled with the correct data by writing directly into this .bit-file. Information where exactly to write and in which format, has to be known by the designer and has to be passed to the Xilinx tools by means of a(n un-placed) .bmm-file. The content of our mblite.bmm is shown in Figure 2.1. 8 CHAPTER 2. ADDITIONS TO THE ET4351_VHD PACKAGE Listing 2.1: mblite.bmmSynpli f yStyle ADDRESS \ _SPACE dram RAMB16 [ 0 x00000000 : 0 x00003FFF ] BUS \ _BLOCK I \ _MBLITE / I \_DMEM/ ram0 \ _ram0 \ _0 \ _1 [ 3 1 : 2 8 ] ; I \ _MBLITE / I \_DMEM/ ram0 \ _ram0 \ _0 \ _0 [ 2 7 : 2 4 ] ; I \ _MBLITE / I \_DMEM/ ram1 \ _ram1 \ _0 \ _1 [ 2 3 : 2 0 ] ; I \ _MBLITE / I \_DMEM/ ram1 \ _ram1 \ _0 \ _0 [ 1 9 : 1 6 ] ; I \ _MBLITE / I \_DMEM/ ram2 \ _ram2 \ _0 \ _1 [ 1 5 : 1 2 ] ; I \ _MBLITE / I \_DMEM/ ram2 \ _ram2 \ _0 \ _0 [ 1 1 : 8 ] ; I \ _MBLITE / I \_DMEM/ ram3 \ _ram3 \ _0 \ _1 [ 7 : 4 ] ; I \ _MBLITE / I \_DMEM/ ram3 \ _ram3 \ _0 \ _0 [ 3 : 0 ] ; END\ _BUS \ _BLOCK ; END\ _ADDRESS \ _SPACE ; ADDRESS \ _SPACE i r a m RAMB16 [ 0 x00000000 : 0 x00003FFF ] BUS \ _BLOCK I \ _MBLITE / I \ _IMEM / ram \ _ram \ _0 \ _7 [ 3 1 : 2 8 ] ; I \ _MBLITE / I \ _IMEM / ram \ _ram \ _0 \ _6 [ 2 7 : 2 4 ] ; I \ _MBLITE / I \ _IMEM / ram \ _ram \ _0 \ _5 [ 2 3 : 2 0 ] ; I \ _MBLITE / I \ _IMEM / ram \ _ram \ _0 \ _4 [ 1 9 : 1 6 ] ; I \ _MBLITE / I \ _IMEM / ram \ _ram \ _0 \ _3 [ 1 5 : 1 2 ] ; I \ _MBLITE / I \ _IMEM / ram \ _ram \ _0 \ _2 [ 1 1 : 8 ] ; I \ _MBLITE / I \ _IMEM / ram \ _ram \ _0 \ _1 [ 7 : 4 ] ; I \ _MBLITE / I \ _IMEM / ram \ _ram \ _0 \ _0 [ 3 : 0 ] ; END\ _BUS \ _BLOCK ; END\ _ADDRESS \ _SPACE ; In case memory sizes are changed, and/or the setup of wb_mblite.vhd is changed (I_MBLITE, I_DMEM and I_IMEM are labels), this has to be reflected in an appropriate new .bmm-file before makebit_bmm can be run. For your convenience, the script makemem is provided: syntax: makemem bitfile memfile where bitfile is the name of the .bit-file just created and memfile is the name of the .mem-file to be inserted. Note: no filename extensions; bit and mem files should be in the local directory, i.e. /rev_#. e.g. ./makemem wb_mblite_uart_soc imem_dmem rom /rev_1 The output file with (re)loaded memory, will be renamed to download.bit The newly resulting .bit-file can be downloaded to the AVNET board using Xilinx iMPACT program. 2.3. SCRIPTS AND UTILITIES 9